SDF(Standard Delay Format)是一种存储timing data的文件，其中的数据是tool-independent的

可以包括：

1)Delay: module path, device, interconnect, port

2)Timing checks: setup, hold, recovery, removal, skew, width, period

3)Timing environment:

 

SDF file支持hierarchical timing annotation, 各个module的sdf文件可以分别提供，整个design有多个SDF files.

 

Back-Annotation of timing Data for Design Analysis.

SDF中的timing data来源：1)直接来自timing model,  2)内部的timing calculator,  3)Cell characterization data

           数据的准确性，与timing caculator内的算法, pre-layout的RC预估. post-layout的RC提取.

Annotator: SDF中的数据反标到analysis和check tool

consistency between SDF and Design：任何design中的修改必须rerun timing calculator,产生新的SDF文件

consistency between SDF and Timing model：lib中的timing model必须和产生的sdf，对数据的识别程度时一样的，

                 否则会导致有的delay反标不上去

 

back-annotation主要是进行analysis timing data，forward-annotation of timing constraints主要用给synthsis tools

(不仅是logic synthsis，还包括floorplanning,layout, routing)

 

SDF支持的timing model：

1)Modeling Circuit Delays:SDF支持distributed(由model primitive来组成)和pin-to-pin(通过lib中的timing property)的model style。

                                      IOPATH-------input to output delay

                                      COND---------condition

2)Modeling Output Pulse Propagation:PATHPULSE------定义非glitch的最短的pulse

3)Modeling Timing Checks:支持setup,hold(反标回lib model), recovery, removal, width,

                                       SETUP (posedge D0)  (COND (posedge CP))  (value1 :: value2)

                                       HOLD (posedge D0)  (COND (posedge CP))  (value1 :: value2)

                   setup/hold的值，可能也是与input transiaction/output capacitance有关，

                                           所以通过sdf反标到verilog model中。

4)Modeling Interconnect Delays: INTERCONNECT---------------point to point的delay

                                                PORT------------针对有几条driver path的signal

5)一些Internal nodes,针对不在design hierarachy和lib中的primitive的path，要求annotator能够识别。

                               提供给个别项目的一种灵活的方式

 

SDF文件的格式：